Telecommunication Circuits ELEC 4505


2005 Course Outline


Exam Review Dec 14, 3-5 in Room ME4499

Term Marks. Note, Total Lab marks assume Lab1, Lab2, Lab3 are scaled to the highest mark ( 111,75,111).

Assignment 3 can be picked up from Peter on Wednesday Dec 7, or Friday Dec 9 between 10AM and 5PM in ME5138

Exam Dec 15, 2-5, Southam Hall

Will solve old Exam Problems Nov 29, Dec 1

Questions, Answers for Assignment 3, Lab 3, E.g., Calculating RMS value, Expected Voltage swing on oscillator? Lock range vs. loop bandwidth? Kphase for phase detector 3 seems off by a factor of 2? last entry Nov 28, 2005

Please feel free to email me with questions, I will attempt to answer them by email, but will also post them here.

Questions/Answers from 2004.

Questions/Answers from 2003

It could be that ELEC 2501 is using the computer room - in this case we hope to leave you a note by the door telling you where the TA will be stationed - possibly in the computer room close to the elevator or MC 6030

Since Nov 23, 24, 25 would normally be lab days, a TA will be available from about 10AM in the computer room across from the lab on each of those days. So, if you want to take advantage of this lab time slot, and do your oscillator SPICE assignment, or have any other questions for the TAs, you can take advantage of this opportunity.

As announced in class, (Thur. Nov 10) Lab 3 due date is now 5 days later, that is, labs are now due on Mon Nov 21, Tue Nov 22 and Wed Nov 23.

For Assignment 3, to be handed out in class, You will need to copy and modify the following two programs for oscillator analysis. Your aim will be to achieve a particular output frequency and power, and being approximately impedance matched. So, what you will need to change:

Assignment 3 Example SPICE file for Open-Loop Oscillator test.

Assignment 3 Example SPICE file for Closed-Loop Oscillator test.

Notice: Assignment two help can be found in the Question list - link back to 2004, 2003. E.g, What to do about 3 equations four unknows? How to deal with 2.5 V?

Lab 2 Marking Scheme, updated somewhat from one used some years ago. (PDF) This may not be quite final yet, but it should give you an idea of what is being looked for. Another example version of Lab 2 Marking Scheme (PDF)

Inductor Q at 100 kHz and 1.2 MHz

SPICE File For mixer This is not required for the lab, but you may find it interesting and useful. Note, this is a nonlinear circuit, so simulations are in the time domain. Tos see output spectrum including harmonics and intermodulation components, run the fft on the output transient waveform. Note that for this simulation, discrete 2N3904 transistors have been used, but in spite of this, the results are quite realistic.

Photo of a Neatly Constructed Mixer Board. Note that pin 7 has been used as an interconnect point. It is labelled on the diagram as NC for No Connect. Often it is not a good idea to use such pins, but in this case it seems to work. (I still wouldn't do it though.) Also, note the yellow wire hides a connection. Don't believe it? Check out this picture from a different angle.

Lab 2, Mixer: Important Points:

As announced in class, Oct 4, Lab 1 and Assignment 1 are due at 1:00, Tuesday Oct 11 in class for all groups, Wednesday, Thursday and Friday

Lab 1 Held in Computer Room, next to hardware lab, ME4166

Lab 1 Approximate Marking Scheme 2005 (PDF)

2005, Course Outline, (PDF)

General Handout (PDF)

Second Page, Overview (PDF)

PSPICE Student Version, exe file (previous year version) (28M)

Click here for to request the orcad demo including PSPICE directly from orcad (part of Cadence) (174M)

Link to the year 2004.

Link to the year 2003.

Link to the year 2002.

Link to the year 2001.

SPICE File For Lab 1.

Lab 1 Information, Posted Sept 23, 2003 (written much earlier)

Lectures: TB 238
Times Tue 1:00, Thur 1:00,
Labs: ME4135, Wed, Thur, Fri, 8:30-11:30 odd weeks
TAs: Peter Popplewell, ppopp@doe.carleton.ca, Tony Forzley, tforzley@doe.carleton.ca
Office Hours: C. Plett Mon, Wed, 11:30-12:30, TAs, TBD

Course Objective

To learn about the design of communications circuits. In other courses, the block diagram approach has been used but in this course the emphasis will be on the actual circuitry which makes up these blocks. Examples of such blocks are tuned amplifiers, mixers, oscillators, phase shifters and detectors. Communications systems considered are AM, FM, television and telephony. Use of the PLL will be discussed.

Course Content

  1. Introduction to Telecommunications: Components of a radio systems; noise, distortion impedance matching.

  2. Mixers and Modulators:

  3. Phase-Locked Loop and Applications: Introduction to PLLs and applications such as: synthesizers and FM demodulation.

  4. Oscillators:

  5. Frequency modulators and demodulators:

  6. Television Systems: Transmission of intensity, color, retrace, blanking, and sound; generation of the video signal, conversion of the video signal to picture and sound. Other topics may include high-definition TV, stereo sound.

Labs

Simulation Labs - Groups of 1; Hardware Labs - Groups of 2, one writeup per group, due one week after the scheduled lab day, 4:30 PM.
  1. Tuned Amplifiers: (Dates tentative) (Warmup on September 15, 16, 17 actual lab on 29, 30, October 1). Simulation Lab. Use of a bipolar transistor and some passive components to build a tuned amplifier operating at about 1MHz. You will learn about use of transistor parameters, tuned circuits and impedance matching.

  2. Mixers and Modulators: (October 13, 14, 15) Use of an analog multiplier on an IC to build frequency changers.

  3. Phase-Locked Loops: (October 27, 28, 29 and November 10, 11, 12) Use of a commercially available package to build a tracking filter, a synthesizer and a an FM demodulator. The IC contains a voltage-controlled oscillator a phase detector, and amplifiers. In this lab, the VCO and phase detector will be characterized, then a complete phased-lock loop will be built. The main external components will consist of a simple loop filter and a divider to realize the synthesizer.

Marks:

a) Three assignments worth 5% each
b) Three Labs worth 10, 10,15 (about 1/3 for demo)
c) One written exam worth 50%.
**** Students must get at least 35% in the final exam. ****

Text:

There is no official course text. The printed course notes should provide enough material, or some of the references can be consulted.

References: