Answer
Question Dec 5 I was just wondering if you could help me out here I was just doing the 1998 Q8 PLL question. It asks to identify the loop filter. the answer provided is LPF. But here is ths problem : I found the A0 = 0.628 (Matches the answer provided) well then how can that be a LPF dosent the filter gain have to be 1 in orgere for it to be LPF. So is the answer provided mistyped and is the right answer: Intergrator with phase lead wit finite DC gain. If not could you explain how to find difference between a LPF with phase lead and interagrator with phase lead and finite DC?.
Answer I believe you are thinking too specifically about the lowpass filters we talked about in class. In general, as long as the DC gain is less than or equal to one, it could be a passive lowpass filter. There is no reason the DC gain has to be equal to one (a simple way to get gain less than one is to realize the first resistor as a voltage divider). However, you can't have DC gain larger than one (at least not easily). However, if you remove the word "passive" and just call it a low pass filter then there is no restriction on what gain you can have at DC. So, for this specific question, the shape tells you it is some form of a low pass filter. With the gain of 0.628, it could be either a passive filter or an active filter (or in fact an integrator with finite DC gain although often we might expect something that was called an integrator to have much higher DC gain.)
Question Dec 5 Does "open loop" refer to just examining the filter response?
Answer No, open loop is the whole loop, Kphase x F(s) x Ao x Kvco/s
Question Dec 5 I got stuck on Q7 from the 1999 final exam. I understand the different ways of interpreting the waveform (AM and DSBSC) but I'm having difficulty with the final step. I've tried many different combinations of RMS voltages but cannot seem to get the answer in the back. I had the same problem yesterday with Q8 from 2000. Can you please explain how I can find the total RMS voltage?
Answer You have to find the individual components first, e.g.,
for AM max = A(1+k), min = A(1-k) then solve for A and k
for DSBSC + filter max = A+B, min = A-B, then solve for A and B
Then knowing the components knowing all are at different frequencies, sum the square of the rms voltages and take the square root to find the overall rms voltage. Note voltages A, B, etc are peak, so must divide by sqrt(2) to get rms.
For AM Vrms = sqrt{A^2/2 +(AK/2)^2/2 + (AK/2)^2/2}
For DSBSC + filter Vrms = sqrt{A^2/2 + B^2/2}
Question Dec 5 Regarding the noise question (Number 2, 2000) I was looking specifically at the gain ratio of the resistor Ri to Vout. I thought that any voltage seen before this resistor would undergo just the x20 and the x1/2. In the notes there was another factor of 1/2. I thought this could only be if we were considering that the voltage at this point was already 1/2 due to the source resistor. But my understanding was that this is a separate analysis and this shouldn't come into play when analysing the Ri resistor (only when analysing the contribution of Rs). So is my understanding correct?
Answer Any voltage source at the input is connected to a voltage divider and so the voltage divider must be applied to it to find the actual voltage vi. From a noise point of view, Rs and Ri are treated the same way. The voltage vi goes from the middle node to ground and each of these two resistors goes from the middle node to ground, so they are treated in exactly the same way.
Question Dec 5
Answer
Question Dec 5 I have a quick question with regards to questions 1a) from the 2002 ELEC 4505 final. It's asking for the input frequency which yields the image that is most difficult to deal with (can't be attenuated fully). It says the answer should be 928MHz yielding an image of 728MHz which makes sense but from looking at the filter diagram I would say that it should extend only to maybe 840MHz on the lower side meaning that anything in the input range should be filtered before the LO mixing stage. Is this incorrect?
Answer The filter is assumed to extend forever at the same rate, it's just that we can't show it forever. And yes, signals are being filtered before getting to the mixing stage, but this is the filter that does it.
Question Dec 5 I was doing question 1, the tuned amplifier, part C when I realized that in your solution you have turned the parallel 1K resistor with the capacitor Cpi into a series 24.7 resistor with a 155.22 capacitor. can you plz explain how you went from the parallel circuit to the series one?
Answer You simply invert the impedance to get the admittance Zin = 1/Yin. At the frequency of interest, both circuits have the same impedance and both circuits have the same admittance (try it), although it is more natural to use impedance to describe the series circuit and admittance to describe the parallel circuit.
Question Dec 4 Exam 1998 No 7: how is theta 60degrees???
Answer Conduction is 10nsec, period is 30 ns. Cond. angle is (10n/30n) x 360=120 degrees, Theta = 60 degrees.
Question Dec 4 And in general for oscillators, we can estimate the freqeucy by X1 + X2 + X3 = 0.. does w=1/sqrt(LC) give same result?
Answer X1 + X2 + X3 = 0 gives the same result as w = 1/sqrt (LC) where C is the series combination of C1 and C2.
Question Dec 4 Exam 1998 1c) to calculate bandwidth do we use : for Rtotal= ro||50trans or is Rtotal = 50||ro transformed
Answer I calculated it with respect to the primary since that is where the capacitor and inductor is. For this reason you transform the 50 Ohm resitance to the this side.
Question Dec 4 I don't understand why do we allow for the effects of non-linearity to occur in Local Oscillators. You've mentioned in your notes that "LO harmonics, or nonlinearities in the LO path will result in the RF signal being modulated around multiples of the LO, but these are easily filtered pg.36". Thinking about this statement and about all the filtering circuits that we see in a receiver circuit, I see that disregarding nonlinearity in LO will generate different RF signals in our spectrum. These RF signals could randomly be very close to other RF signals that are to be selected by some other receiver, thus creating the problem of non-linearity somewhere else in our frequency spectrum. Although this is random, why should we allow for it in the first place ?
Answer Nonlinearities around multiples of the LO are far away from the LO (e.g., LO at 1 GHz, harmonic at 2GHz, 3GHz). Compare this to the RF which could be 902 MHz, 904 MHz, 906 MHz, etc which could intermodulate. LO harmonics cannot be close to this RF frequency. The only time we get into trouble is if we have input signals at twice or three times the LO minus the IF frequency, e.g., in our example around 1900 MHz and 2900 MHz and these frequencies are easily filtered out by the image reject filter. We don't mind the LO being nonlinear, because we use the mixer as a switching input and so the mixer itself makes enhances this nonlinearity. We note that this switching is allowed or encouraged because it helps the mixer performance (increases gain, decreases noise, removes effect of amplitude variation on LO signal).
Question Dec 3 Is it still possible to choose the alternative exam for Monday December 8?
Answer Yes, as long as you have a legitimate reason and you let me know by early Friday I can add your name to the list. A typically legitimate reason is having one or more other exams very close to the Dec 6 exam.
Question Dec 3 Is there any way to get the abbreviated answers for the 2002 and 2001 exams?
Answer The solutions to the 2001 exam is now on this web site (it was previously avaialable on last year's web site), I'll try to put abbreviated answers for the 2002 exams on this web page shortly.
Question Dec 3 In the 2000 exam, question 1(c) asks us to compute the output impedance. It seems to be ro||rp, and then transformed. My question is why do we not include the resistance due to the transformation of the 50 ohm load resistor to the primary side?
Answer We are trying to find the impdedance as seen from the view point of the 50 Ohm load resistor. Thus we look into the transformer and see what is on the other side of it. The 50 Ohms would be transformed only if were calculating the impedance from the view point of the collector.
Question Dec 3 Question 1(a) of the 2002 exam says that the filter is a 4th order, but it is only falling off at 40 dB/decade, which implies 2nd order to me. Was this a typo? In the same question, I found the image frequency to be 728 MHz. The question asks us how much attenuation the image filter provides at this frequency. How do I figure that out analytically?
Answer A fourth-order bandpass filter has a second-order rolloff on both edges rather than a fourth order on one edge. This can be seen by its equation which is of the form s^2/(s^4 + ..... a). Thus at low frequency as s goes to 0 we get s^2/a which rolls off as a second order. At high frequencies as s goes towards infinity the equation is s^2/s^4 which again rolls off as a second order.
Another equivalent way to look at it, and the way to solve this problem, is to consider that fourth-order BPF is equivalent to a second-order LPF which has been transformed or translated into a bandpass filter. Thus a BPF with a bandwidth of 26 MHz is equivalent to a LPF with a bandwidth of 13 MHz (the centre frequency has been translated to 0 Hz. Then any offset is done with respect to this 13 MHz equivalent lowpass filter bandwidth. Thus if the LO is 100 MHz away from the RF, then the image is 200 MHz away, and worse case, the RF is at 928 and the image is at 728 MHz as you say. This relative to the passbend edge at 902 MHz is 174 MHz away. Then, we need to calculate the number of decades and this is simply log(174/13)=1.127 decade. Then the attenuation is 40 dB/decade x 1.127 decade = 45.0 dB.
(Final note: I dind't cover this in class this year, so I wouldn't expect that you would necessarily have been able to solve this.)
Question Dec 3 Question 1(c) of the 2002 exam asks us for a noise type of thing. It states the gain as being 15 dB. To convert this to a linear number for use in the noise formula, should I use the voltage formula (20 log x) or the power formula (10 log x)?
Answer Noise Factor = No,total/No,src where No,total and No,src are noise power, so it is appropriate to use 10 log. Also, No,src = G Nin and here G must be power gain.
Question Dec 3 I remember that you discussed in class how a reactive component adjusts the real part of the total impedance. I was going through the matching and found that this is evident only when the expression for the total impedance is converted to admittance. for example:
ZL=20+j10 <<
convert into admittance:
Y_in = 1 / (ZL+jwL) = (ZL- jwL) / [ZL^2+(wL)^2] =
ZL / [ZL^2+(wL)^2] - jwL / [ZL^2+(wL)^2]
in admittance form the reactance of L is in the denominator and
numerator has Real and Imag parts.
Could you please explain again how it works that L or C changes the
resistive value ?
Answer
It isn't just one component, but actually because we place two
components in general, typically one in series, one in parallel.
Both components were purely reactive, yet the real part of the
impedance is changed. Mathematically, for both ways of impedance
matching we needed at some point to convert from parallel to
series or series to parallel, and at this point we can see the
change of real part. As an example, for real part less than
50 Ohms, we added a series inductor then we converted this series
circuit to an equivalent parallel circuit and at this point we
we saw an expression of the following type:
Y2 = (R -jwX)/(R^2 + X^2)
thus the original real part which was equal to R is now modified
by R^2 + X^2. X included the original imaginary part, but also
the new series inductor, so we can adjust this value to arrive
at any real part we like.
A similar expression can be found for the case where we added
a parallel capacitor. Then we had something like:
Z2 = (G-jY)/(G^2+Y^2)
where Y included the admittance of the parallel capacitance.
Thus once again, the capacitance has modified Y, and the real
part of the above expression which was originally G is now
G/(G^2 + Y^2), and so we can adjust this added capacitance to
get any real part that we like. So, in both cases, we add a reactive
part, then invert the expression to convert between a series
and a parallel circuit.
In class I related the first case above to the equations relating
a series LR circuit to a parallel LR circuit. For the equivalent
parallel circuit with the same Q, rp = rs(1+Q^2), where Q = wL/rs.
So for a fixed series resistance of rs, the value of parallel
resistance rp can be changed simply by changing the inductance,
(by adding a series inductance to our circuit). We note that,
as above, this change of resistance is only seen in the conversion
of series to parallel, but to complete the matching this is what
we need to do since the next step would be to add a parallel
capacitor.
Question Dec 2
what kind of equation sheet we would expect to see for the final.
Will it be similar to the "crib notes" in the back of the course notes
(page 168 to 170)?
Answer
It is almost exactly like page 150 "97.455 Formuala Sheet", so
it is a good idea to practice solving problems using this formula sheet.
Question Dec 2
I was just doing the 1999 exam Q9 (PLL) in section a) we are asked to
find the damping constant, center frequency and the natural frequency
in such a way that the PLL bandwidth is 100KHz....
How do I go about doing that... I have assumend the damping constant
to be .707 so do I just use the formula from the sheet
(B<=2(omega_n)(damping constant)).. the answer obtained this way
dosent match with the answers on the solution posted on the site with
the abbrivated soultions for old exams. (The answer posted is: 6a)
damping = 0.707, f_0 = 67.2 Mrad/sec, omega_n = 444.4 krad/sec).
Answer
It sounds like you have nearly answered your own question. You
have the correct equation for bandwidth which is that (B<=2(omega_n)(damping
constant)). Then you select damping constant is 0.707, then knowing
what you want bandwidth to be (100 kHz) , you can calculate the
remaining unknown which is omega_n = B/(2 x damping constant)
= 2 x pi x 100k /(2 x 0.707)= 444.4 krad/sec.
Question Dec 2
My question concerns Q1 on the 1998 exam. It deals with the tuned
amplifier. I got parts a and b but I am having some trouble with
part c. The equation for gain that I get is
vo/vi = -gm (ro||rtransformed)(1/8)
where the 1/8 is from the transformer. Pluging in the values
gets me no where near the answer of 7.5 given in the book. Do
you have any suggestions on solving this problem? Do I have to
transform the 50 ohm resistor?
Answer
Your own equation should give the right result, and yes, rtransformed
which you have shown in your equation should be in your equation. What
value did you use for it? Basically you first calculate vc/vi = gm x
Requiv, then you calculate vo/vc = N2/N1.
Question Nov 30
I am havinga bit of trouble with plotting the magnitude of the
PLL's..i might be on completely the wrong track though....here's
where my confusion is:
On p. 63 of your notes..there is a plot given which is plotting
the 1-st order PLL given by K/s+K...the way i see it, the bode
plot of this would be 0dB until omega=K and then the graph falls
with a slope of -20dB/decade after that. Realizing that the
plot you hve given is in log-log scale..this means that there
should still be a constant at 0 until omega= K and then
slope of -1 after that... that's not what it seems like!!
Of course this confusion extends into the second order plots
but i'm hoping once the 1st order plots make sense, the others
will follow..
Answer
You are right - once you understand this one you should have
no problem with the other ones.
We are plotting open-loop gain, which is LG=K/s. What you are
thinking of is closed-loop gain which is
CLG = FG/(1+LG)= (K/s)/(1+K/s)=K/(s+K).
LG is what we need to predict stability.
Thus, K/s has constant slope of -1 on a log-log plot and a phase
of -90 degrees.
Question Nov 29
I was working though the 2001 exam and had a couple of questions..
Answer
Question Nov 27
Any idea yet what went wrong with that question you did in class
today?
Answer
Not completely verified, but I am now fairly certain that the
copy of the exam as printed in the course notes is not quite
the final version of this exam. What I believe happened is that
at the time this exam was being made up, I was helping to make
corrections to this exam. Upon checking my records I discovered
that that the exam printed in the course notes is one to which
I made a number of corrections, but it is not the corrected one.
I am waiting to get the final copy of the exam, then I will post
it and the correct solution to the particular problem we were
solving in class.
Answer
I think the second assignment is marked, but the TA has not yet
delivered it, or the marks, back to me. I hope to get it to you
Tuesday, but maybe Thursday. The last lab is being marked, but
it will take at least a few more days to complete. The last assignment
should be very speedy to mark, so I expect marking to be completed
by early next week. However, it can't do any harm to photocopy
it just to be sure.
Question Nov 23
In assignment 3, question 2, I took into account the effect of
IB by assuming a beta=100. Is that right or should i just ignore
IB and assume it's negligible when doing the voltage divider?
Answer
There is never anything wrong with including it, stating that
you assumed beta = 100. However, beta is quite variable, and
if the bias current is significantly higher than the base current,
you won't be that far out if you ignore it. So, either way will
work as long as you state what you assumed.
Question Nov 23
I just wanted a clarification on what startup tranisent is.
Is it the time taken to reach a stable voltage?
Answer
That is almost the answer I would have given. I would probably
say the startup transient is the voltage versus time waveform
starting from the time the voltage first departs from 0V up to
the time the waveform has settled (or reached a stable voltage).
By this definition, if the waveform just sits there at 0 V for
quite a while, I would not include it.
Question Nov 22
For assignment 3, Q2. part b (RL calculation) you mentioned that the
peak-to-peak outpur voltage will be about the same as Peak-to-peak
voltage at the collector. The collector voltage is nominally at Vcc
with a peak downward swing to about Ve. My question is when you say
"nominally" does it mean that the highest value the sine swing will
reach is 5V (avg = some +ve #) or is it that the sine wave is sitting
at 5V (like is the avg V = 5). So basically does it look like this:
Answer
Nominal voltage is another term for average voltage which is also the
same as the DC component of the voltage. It has to be 5 V since the
output is connected to 5V with an inductor. As a result, the output
voltage waveform cannot be as you have shown in a) because it does not
have an average or nominal value of 5 V. But the output waveform could
be b) because it does have an average or nominal voltage of 5V.
Question Nov 22
My open loop simulation and closed loop simulation result in
different values for oscillating frequencies. Should I adjust
C1 and C2 to bring them to the right frequency?
Answer
No, predict your frequency using X1 + X2 + X3 = 0. Then simulate. I
expect the open loop prediction of frequency will be a bit lower than
the calculated frequency (think of the effect that transistor
parasitic capacitance would have). So, if it is close but not
quite the same, simply comment on why there is a difference.
If it is a long way off (e.g., if it is off by 20%), then go
back to see if you have made a mistake in your calculations or
in translating calculations into a SPICE netlist. Similarly,
the closed loop actual oscillating frequency will be shifted
from both the prediction and the simulation, but again not by
that much. So comment on possible or likely causes for the shift
(e.g., large signal versus small signal behaviour, additional
phase shift due to nonlinear distortion) Again, if the actual
oscillating frequency is off by a lot there is probably a problem
somewhere.
Question Nov 22
I had a quesetion about assignment 3. In 2 (ii), it says that Rl is
matched to rp and Req. This Req, i'm assuming, is the equivalent
resistance seen from Rl...that would be Re + (R2||R1||rpi)(beta +
1)..then howcome in the Req given, the R1 and R2 are not mentioned at
all?
Also, the equations we are solving to get c1 and c2 are:-1/jwC1 -
1/jwc2 +wL1 = 0 and the one implied by the matching, right?
Answer
You had me puzzled for a while by your question, but I may have
figured out why you are confused. The assignment says quite clearly
that Req = (re + Re) x (C1/Cs)2, so I was not sure why you would think
it would be something different, but I guess you are trying to see
where this comes from? As well, I couldn't figure out why you would
multiply anything by (beta +1) as this is usually used to move
impedances from the emitter to the base. We aren't interested in
anything on the base, in fact we have placed a large capacitor on the
base to make sure everything there is shorted out (including R1 and
R2). I believe you may have meant to divide by (beta +1)? In that
case, we can divide rpi by (beta +1) to get re, then you are on the
right track, but R1 and R2 do not enter the equation because of the
base capacitor. However, this is not the complete answer since we must
then determine the equivalent resistor which is seen at the collector
of the transistor.
So, let me go over this carefully. On the emitter we have re + RE.
This is in parallel with C1. Looking into C2 we see a complex
impedance given by C2 in series with the parallel combination of re +
RE and C1. It can be shown that this is equivalent to a capacitor Cs
in parallel with a resistor Req where Cs is approximately the series
combination of C1 and C2 and Req is equal to (re + RE)(C1/Cs)2. The
capacitor Cs will resonate with inductor Cl so all that is left is the
resistance, thus the load resistor Rl must be matched to the parallel
combination of Rp and Req.
Thus, it turns out that the frequency is given by the series
combination of C1 and C2. Impedance matching is dependent on
the ratio of C1 to C2 (or equivalently C1/Cs), so it is not difficult
to come up with values for C1 and C2 that satisfy both conditions.
Question Nov 21
I know in class you used the spring analogy for explaining why
the output voltage can go above the power supply rail. Can this
also be explained by energy transfer between the inductor and
the capacitor?
Answer
Warning - this answer drifts off topic a bit,
and although is is not terribly complicated it is outside of
the scope of this course. Yes, in fact that is the correct
way of doing it. The oscillator (as well as the tuned amplifier)
has a parallel resonant tank at collector of the driver transistor.
In a tuned amplifier, the cpacitor is directly across the inductor,
both going to the power supply rail, but even if the capacitor
actually went to ground, the capacitor and inductor would still
be in parallel since the power supply is also ac grounds. (The
capacitor blocks dc so it doesn't matter what the voltage is
as long as the impedance is low, i.e., ac ground). In the common-base
oscillator, the inductor goes to the power supply and the capacitor
is the series combination of capacitors going to ground. These
two capacitors in series have another purpose which is to feed
part of the signal back to the emitter of the transistor.
Now for energy transfer, let's assume the capcitor is directly
across the inductor to the power supply rail just to simplify
the discussion.
If we start where the voltage is lowest, at this point energy is
stored in the electric field across the capacitor, but at this point
there is no current in the inductor. However, due to the voltage,
current starts to increase through the inductor and the voltage
across teh capacitor starts to decrease as the ouput voltage
increases. When the output voltage is equal to the power supply
voltage, there is no longer any charge on the capacitor, its energy
has all been transferred to the inductor. This is the point where the
inductor current is maximum hence the energy stored in its magnetic
field is maximum. Current keeps flowing in the inductor and this
keeps charging the capacitor so the output voltage goes past the
power supply voltage. This increasing voltage across the inductor
causes the current to decrease, and so energy is being transferred
back into electric field of the capacitor. Eventually the inductor
current goes to zero and the capacitor is no longer being charged,
but the output is now at its maximum voltage, and all energy is now
in the electric field. This voltage across the inductor starts
current flowing in the opposite direction across the inductor and this
current discharges the capacitor once more and energy is transferred
back to the inductor.
What about the case where the capacitor goes to ground? In this
case the energy in the capacitor is not zero when the output
voltage is equal to the power supply voltage. We can see this
as the nominal energy or the bias energy but we are only interested
in the change of energy away from this bias point. As the output
voltage increases, more energy is in the capacitor, when the
output voltage is lower, there is less energy in the capacitor,
so there is still energy that is moved in and out of the capacitor
and this difference of energy is transferred back and forth between
the capacitor and the inductor. So, the conclusions are still
the same as long as we talk about the difference in energy.
Also note that if there were no transistor, the oscillations
would die down since some energy is lost due to inductor series
resistance and other resistances in the system. In such a case,
the output voltage excursions away from the power supply voltage
would decrease and eventually the output voltage would just stay
at the power supply voltage. When the output voltage is lowest,
it also results in the lowest emitter voltage, this turns on
the transistor which draws current out of the resonant tank circuit
pulling the voltage down even further and in the steady state
this compensates for the loss of energy.
An interesting question is if this would still work if the capacitor
was equal to zero (or at least very low), that is if there were
only an inductor. We start the current flowing through the inductor
by turning on the transistor and pulling the voltage low. Without
capacitance the voltage comes down rapidly, but current ramps
up in the inductor as i = integral V dt, so for constant V, current
ramps up linearly. Then if the transistor is turned off suddenly
(large di/dt), the inductor has all this energy stored in it
(1/2 L i^2) and it would like to dump it somewhere, so it will
try to keep the current flowing. As a result the output voltage
will go up to very high levels in an attempt to keep the current
flowing - essentially this is the way cars generate high voltage
to send an arc across the sparkplug gap to ignite the fuel.
So, yes, without capacitance the voltage will go above the rail,
probably catastrophically. If the transistor is turned off more
slowly, there is still di/dt but it is in the opposite direction of
when the transistor was turned on, so the inductor voltage is also
opposite of the previous case, so this voltage across the inductor
will guarantee that the output voltage is above the power supply
rail. I also note that with a few extra components, (a diode
and a capacitor) this can form a switched-mode boost power supply,
which produces an increased output voltage whose level is dependent
on the switch duty cycle.
Question Nov 18
I'm having a bit of trouble getting all the equations for the
open loop analysis. Can you give me some hints?
Answer
Yes. I didn't want you to do a hand calculation of open-loop
gain. It is possible to do, but is somewhat more complicated
than what I did in class. One of the point of this exercise is
to show that as circuits get more complicated, an open-loop analysis
is still very easily done with a simulation package. Thus, both
the open-loop analysis and the closed-loop analysis are to be
done on the computer using SPICE. I have provided a sample SPICE
file for each of these cases. The only hand analysis you are
supposed to do is to predict output swing and use to set the
load resistor, determine capacitor values to give the right frequency
and impdeance matching to the load. Then you verify with the
two simulations, making appropriate observations and comments
about theory versus open loop versus closed loop, etc.
Question Nov 19
Can we leave out the inductor parallel resistor for the open
loop analysis?
Answer
No, it is quite significant since it is 10k and the desired output
impedance is of the order of 5k. And since this is done by computer,
it doesn't add any complexity to the analysis.
Question Nov 18
Do we expect theory, open loop and closed loop analysis to result in
the same osscillation frequency?
Answer
No, and some reasons for discrepancy could be
Answer
This information is partially in the course notes, was covered
during the lab preparation lecture, and is also in the lab manual:
assuming a 5V supply:
Question Nov 12
In Part 2 of the lab, number 13..it asks for the relationship
between the frequencies at which the PLL loses lock and the loop
bandwidth of 2000Hz..i'm not sure how to go about doing that..
Answer
On Tuesday Nov. 11, I discussed this and wrote the answer to
this on the board at the start of the class - did you miss this?
In any case, here is an abbreviated answer: lock range is a DC
phenomena which depends on the loop gain K (if the lock range
is limited by the phase detector). Often, however, (and this
probably happened in the lab) lock range is limited by the VCO
range, so it has nothing to do with loop bandwidth. On the other
hand, loop bandwidth is determined by omega_n and damping constant
which are dependent to a large extent on the filter time constant,
that is, no matter what K is, we can set our time constant to
get whatever loop bandwidth we want.
Question Nov 12
Are we required to show all our derivations (all the transfer
functions etc.) that we found in assignment 2 again in the lab
write up?
Answer
You should probably show the derivations - this is why we wrote
at the top of the assignment "be sure you save your calculations
for the lab". If you haven't saved them, at least show the outline
of your derivation, that is, don't just write down the answer,
at least write down the starting equations, even if you then
go for the answers. - It actually isn't that difficult to derive,
especially if you have done it before.
Question Nov 12
I have a question about the 3rd lab as the subject line alludes to.
My problem is in question 21 it says that the transition speed of the
filter is determined by the slew rate when we are switching from 800
to 600 kHz. I am a little unsure about what this would look like, I
know that we should have some ringing and some settling time between
the switch from 800 to 600 kHz but I don't understand how the slew
rate fits in. I think the reason for my confusion is that in the lab
we couldn't get this part to work and we had to look off someone
else's scope but they weren't displaying the VCO but the control for
the VCO unless it is the control that the question is asking about.
Answer
The control voltage tells you what is the instantaneous frequency of
the VCO which can be estimated by:
omega_vco = omega_nominal + K_vco x vc.
So, the control voltage is what we need to look at to see the
switching behaviour. If the loop does not lose lock then we can look
at the loop phase error time domain plot as an indication of when the
switching is completed, and how much ringing there will be. From the
curve, we can estimate that settling time is given by the expression
omega_n x t_settling is about 4.5 or 5. In this case, there isn't
anything we would call slewing. If the loop loses lock, then
switching will probably take longer and will be determined by
how fast we can change the control voltage which will probably
be determined by how fast we can change the voltage on the loop
filter. I'm not sure if this is completely correct, but I would
expect to see a ramp of voltage on the capacitor of the loop
filter given by Delta V/ Delta t = i/C where i is the current
coming through R1 the input resistor of the filter and C is the
integrating capacitor C.
Question Nov 12
Is there a difference between synchronization and lock?
Answer
I use the two terms interchangably, for example "synchronization
range" was intended to mean the same thing as "lock range". However,
some people take synchronization to mean phase synchronization, where
the phase of two signals are locked to each other. In a phase locked
loop, usually the frequency is locked, but the phase is the driving
mechanism to cause the frequency to lock - and as the intput frequency
changes, the output frequency remains locked to it, bu the phase
varies to provide teh required control voltage. Thus, phase is
not constant as we change frequency, in other words the phase
is not locked, the frequency is locked. Other uses of the term
synchronous sometimes implies phase lock (e.g., synchronous detection)
but otherwise do not (e.g., a synchronous motor is synchronized
with 60 Hz power line frequency, but from what I remember of
power engineering, the phase is not constant, especially with varying
load.)
Question Nov 8
A question about the lab: The frequency of reference input to
the PLL was incremented/decremented manually through the signal
generator. At each frequency, the phase difference between output
signal and the input reference was measured. (At all these frequencies
the PLL remained locked to the frequency of the input signal).
Does the changing phase shift originate in the transient response
of the PLL to these sudden frequency changes (steady state error
voltage) ? Is there another mechanism that also contributes to
this varying phase difference?
Answer
What you are observing is the steady state phase difference,
since by the time you look at the scope, everything is stable
(the transients only last for milli seconds, since the loop bandwidth
is of the order of 2 kHz). This steady state phase error is
just that phase error which produces the correct error voltage
and hence the correct VCO control voltage to move frequency by
the correct amount to follow the input frequency change.
Now, for the transient - during a frequency step, if the step
is small the new frequency causes a ramp of phase into the phase
detector. The phase detector responds by putting out an increasing
error voltage, hence a changing control voltage which shifts
the frequency of the VCO. If the feedback polarity is right and
the loop is stable, this will bring the VCO in line with the
input frequency.
Question Nov 8
While writing the Lab 3 report, we found what looks like a typo
on page 138 of the lab manual (2003 version). For item 20) it
states that the frequency relationship of the VCO output
should keep exactly at 6:1 and 8:1. But the available N's in
the board are 3 and 4, and this should yield 3:1 and 4:1 ratios.
Answer
Thanks for the note - yes you are right - this happened because
earlier we had been using an additional divide by 2 after the
3/4 divider. Without it, the duty cycle of the divide-by-3 is
not 50%. This matters for the exclusive or-gate phase detector,
but the loop still works without it so later it was decided
to leave it out for simplicity.
Answer
Whoa - I hadn't intended that anyone would try to solve lots
of equations for this one. I expect people will choose a damping
constant, then solve for required omega_n using the required
settling time using the settling plot in the notes as guidance.
Then, this value is used to verify that the phase error is not
too large (again using the settling plot to identify peak phase
error). If it is, then a higher damping constant may need to
be used. Thus it may require a second iteration, but all the
steps should be straight forward.
Question Nov 3
My question is about question 4. given in the question is ep
= pi/4, delta w = 2*pi*50K, and tsettle = 40usec. or so I believe.
To solve this question, solve for wn and Zeta, do I select a
value for zeta, then use the graph on p58 of our notes to get
wn. also We are asked for the minimum freq step to that would
cause us to lose lock. Using and EXOR gate as the PD, with a
max phase error of 45 degrees, were is theta nominal at 45 degrees
or 135 degrees?
Answer
Yes, selecting zeta, then solve for omega sounds good. Your
last question indicates that some clarification is needed as
theta_nominal is neither 45 degrees nor 135 degrees. If we assume
a high loop gain (valid for integrator with phase lead correction)
then the nominal phase (before the transient and after settling)
is plus or minus 90 degrees. The listed 45 degrees of phase error
is not theta_nominal but is the maximum phase error *during the
step*. This 45 degrees away from the nominal does not cause us
to lose lock. For some bigger frequency step, the phase shift
would have been 90 degrees and then we would have lost lock -
and your job is to calculate how big this step would have to
be.
Question Nov 3
My question is about question 5, we have two unknowns, wn and
Zeta, and one equation, ep = (delta w/wn)(1/2zeta). Are we supposed
to choose for Zeta?
Answer
No, this is an analysis question, not a design question. There
are two unknowns and two pieces of information supplied - the
frequency at which phase error is maximum and the value of that
phase error.
Question Oct 31
When finding component values, it seems I have two equations (one for
omega_n one for zeta) but I have three variables, R1, R2, and C. (I realize
that R3 is related to R1 by the DC gain.) What do I do?
Answer
You will have to pick one component, then solve for the other ones. A
constraint should be that component values are reasonable, that is aim for
resistors between a few k and hundred k if possible. (R3 will
probably be large, R2 will be small).
Question Oct 31
I'm having trouble as my calculation shows that one of my resistors has to
be negative - any ideas?
Answer
One thing I have seen happening is that some people have a negative
sign in front of the s term in the denominator of your transfer
function - this will result in an unstable circuit (and potentially
unrealizable components). Typically this happens because you
have positive feedback - for example, if you have an inverting
filter (as you do) unless you change the polarity of the phase
detector, or the polarity of the filter the circuit will be unstable.
Question Oct 29
I have a question regarding the first question on the Assignment
2 In deriving the loop filter transfer function F(s) with 2.5V
at the positive input terminal of the op-amp, I can't seem to
get F(s)=vo/vi on one side of the equation alone. Do we use
a voltage of 2.5V at the negative terminal?(assuming infinite
gain op-amp then v+ = v-)
Answer
To simplify the calculation you can just assume that the positive
terminal is at "AC" ground. You are trying to calculate the
small-signal transfer function and thus 2.5 V DC is AC ground.
This should help...
Then the operating point is 2.5V, but the transfer function only
accounts for the small-signal variations around 2.5V. Note, this
is like the VCO where the nominal frequency is omega_nom and
the full equation is omega_out = omega_nom + K_vco x vc, but
when we write the small signal equation equation, we leave out
the constant term and write only omega_out = K_vco x vc, or theta_out
= K_vco/s. This is also like a BJT amplfier where we write v_o/vin
= gm x RL even though the output voltage may nominally be at
15V, but we are only looking at the small signal deviation away
from the nominal voltage. And the final example, directly relevant
in this course is the phase detector which has a nominal output
voltage of 2.5 V and a nominal input phase of 90 degrees (if
it is the exclusive or gate) yet we happily write ve = kphase
x (theta_o - theta_i).
Answer
I'm not quite sure I follow what you are asking. The amplitude of a
sine wave in the time domain should be equal to the amplitude of a
sine wave in the frequency domain. I have mentioned a factor of 1/2 in
a few places, but that was not one of them. Where a factor of 1/2
occurs is:
I also note that if you treat a sinewave as a phasor, then
you can think of a sinewave as two phasors rotating in opposite
directions, each with half the amplitude. One of these occurs
at f the other at negative f. However, Engineers usually deal
with real signals as can be seen on a spectrum analyzer, which
doesn't show negative frequencies. So, there is no factor of 1/2.
Question Oct 14
I was looking at the lab 2 marking scheme and for step 8 it says
to re-tune the tank so that it picks out the lower sideband of
the mixed signal. In the lab however, we were told to simply
change the carrier frequency so that the lower sideband fell
into the tuned tanks tuned region. This was suggested to save
time. Will marks be deducted if we put the changed carrier frequency
version in the lab?
Answer
As I mentioned in the class, this is the 2000 marking scheme,
not the 2003 marking scheme. It will be approximately followed,
but not exactly followed. And tuning your frequency is effectively
equivalent to changing the tuned circuit - both accomplish the
same task of picking out the other sideband. So this is perfectly
acceptable, in fact it is the new suggested and preferred method.
Howver, since it says in the lab to change the tank circuit,
we also have to give full marks for people who do it that way.
Question Oct 14
Here's a quick question about Lab 2. The equation given in the
data sheets for the low-level AC gain...is that for both the
sidebands? Also, what is the significance of the carrier null?
Answer
It is described in the text around this equation box, some of
the description is to the right of the equations. It turns out
the equations are all for the single-ended output for each sideband.
Whether the carrier is there or not shouldn't make a difference
to the sidebands. However, setting carrier null makes sure the
mixer is balanced. This may help to make sure that the two sidebands
are of equal amplitude.
Question Oct 11
I couldn't get the lab done in my lab period and even though
I came in later, I didn't get to filtering the output sidebands.
Now I don't believe I will have time to come in next week to
get it done. How can I salvage some marks for this part of the lab?
Answer
If you can, try to get into the lab. However, if you can't, there is
an alternative. You could use the PSPICE deck for Lab 2 given
on my web page, modify it to include the output filter and do
the simulation. This can give you output time domain waveforms.
Similar to what you can do in the lab, you can use the PSPICE
FFT function and get the frequency domain response as well. *
See note below regarding fft.
If
you use realistic component values (33 uH with a Q of 45) your
results should match what we see in the lab. If you do a good
job of this, and write it up clearly, you should be able to get
a significant portion of the marks allotted for this part.
* Note about fft in PSPICE - PSPICE fft seems to work for simple
harmonics, but I couldn't get it to work for the mixer. Earlier
versions of SPICE only allowed 10 harmonics, while the frequencies
we are interested in are 850 kHz, 900 kHz, 950 kHz which are
the 17th, 18th and 19th harmonics of 50 kHz, so earlier versions
of SPICE could not handle this, but I thought PSPICE was more
advanced. It is always possible to export the time domain data
to a math program like MATLAB. If someone figures out how to
get PSPICE to do the fft directly, let me know.)
Question Oct 11
I'm trying to do the calculations for lab#2 and I need the Output
Resistance of the Modulator (for calculating the parallel combination
of the RL, rp and the modulator resistance), however, on the graph, it
is not given at 900KHz. Am I supposed to interpolate? If so, how
would I go about doing that?
Answer
You could extrapolate (not interpolate) but we are just guessing
which way the curve goes. Since the output impedance is listed
only for higher frequencies, I would assume this means the impedance
is higher at 900 kHz. However, to be safe I would simply estimate
the impedance to be equal to the first specified value. It should
turn out that it is much higher than the other components you
have across your resonant tank (e.g., the parallel resistance
due to the finite inductor Q).
Answer
What happens is that the current waveform is nonlinear, especially
if you have designed it to operate as class C where the current
goes to zero for a part of each cycle. Any nonlinear waveform
has harmonic components including the second harmonic. Then we
use a parallel tuned circuit as a filter at this frequency to
give us an output voltage at 2 x f_in and filter out all other
frequency components.
So, in other words, the current has all the frequency components,
but only the current component at f_o is at the frequency of
the resonant tuned circuit and this current component will be
turned into an voltage as v_out = gm x R_L. Other frequency components
are shorted out to V_CC (V_CC is an ac ground). These other components
have an output voltage of gm x Z_L but unless you are at resonance,
the impedance is not equal to R_L but R_L in parallel with the
impedance of the capacitor and the inductor and this will be
much lower, close to zero, so the output voltage at these other
frequencies is zero.
Question Nov 24
Will we be getting the 3rd assignment back before the exam?
Just wanted to know if I should make a copy of it and keep it
for reference. Also, not seem pushy or annoying but when will
be getting the 2nd assignment and last lab back? Just curious.
a)
+5 . .
. .
v--------------------------------
. .
+Ve . .
OR b)
V . .
. .
+5--------------------------------
. .
+Ve . .
I'm not sure, but there may be some questions/answers on this
topic in previous years. There is a link to these on the web
page, but I hope to add any relevant comments later.
Question Nov 13
Where do we get the theoretical values for Kphase? Are they just
the ones provided in the assignment, or were we supposed to find
them somehow?
Question Nov 3
I am trying to solve question 4 analytically, which I think should
work since it has two unknowns (omega_n and zeta) and two requirements
(settling time and phase error during the step). However, I'm
having some trouble since I'm not sure of the mathematical relationship
between zeta and settling time. Can you give some help?
Question Oct 14
Just wanted to confirm..the weights of the delta functions in the
frequency domain represents the amplitude/2 of the time domain
waveform..right?
Question Sept 28
I just wanted to ask you a question about part 2 of lab 1 (frequency
multiplication). What does the "multiplication by 2" really mean? I
mean I know the input should be 4.5MHZ so that the output is 9MHZ. But
is there an explanation for this? Last Wednesday you said something
about currents but I seem to have forgotten about it. Thanks in
advance.