Telecommunication Circuits ELEC 4505


2003 Course Outline


Exam Date: Saturday Dec 6, 9:00. Southam Hall, Level 4,5, or 6.

Alternative Exam Date: Monday Dec 8, 9:00, ME 3190.

So far there are about 16 people signed up to write this exam. If you would like to write the alternative exam, let me know by email before Friday noon. (Please indicate which other times Thurs, Fri, Sat you are writing exams).

Assignment, Lab Pick Up, Fri Dec 5, 11-2 ME 5146 (my office)

Answers to Final Exam 2002.

Solutions to Final Exam 2001.

Q & A Session 11:30-1:00 in our classroom, Tuesday Dec 2 based on the following vote.

Office Hours Tuesday, Thursday 9:30-10:30

Please feel welcome to drop by to ask questions, make comments, have discussions on 4505, (or any other topic).

All Marks as of Dec 4, 2003. Please check over and let me know if there are errors (we've already found some)

Assignments, Labs Returned: We hope by Monday, Dec 1. Stay Tuned

Questions, Answers for Exam Review, Assig 3, Lab 3, Assig 2, Lab 2, Lab 1, Assig 1.

Please feel free to email me with questions, I will attempt to answer them by email, but will also post them here. Also, click here for questions and answers from 2001. This link (and link to 2002) can also be found about 17 lines down.

Assignment 3 (pdf)

Assignment 3 SPICE file for Open-Loop Oscillator test.

Assignment 3 SPICE file for Closed-Loop Oscillator test.

Assignment 2, due in class Tuesday November 4. (PDF)

Marking Scheme for Lab 3 (PDF)

Marking Scheme for Lab 2 from 2000, Mostly still the same, except demo was not done formally. (PDF)

SPICE File For Lab 2.

Marking Scheme for Lab 1, Assignment 1 (PDF)

2003, Course Outline, (PDF)

Second Page, Overview (PDF)

PSPICE Student Version, exe file (28M)

Click here for PSPICE download directly from Cadence

Room Number: 3269 ME

This room has 68 seats for about 75 students - it wasn't crowded for the first class, but crowded for later classes.

Link to the year 2002.

Link to the year 2001.

SPICE File For Lab 1.

Lab 1 Information, Posted Sept 23, 2003 (written much earlier)

Lectures: ME 3269
Times Tue 11:30, Thur 11:30,
Labs: ME4135, Wed, Thur, Fri, 8:30-11:30 odd weeks
TAs: Peter Popplewell, Hesham Ahmed
TA Office Hours: TBD

Course Objective

To learn about the design of communications circuits. In other courses, the block diagram approach has been used but in this course the emphasis will be on the actual circuitry which makes up these blocks. Examples of such blocks are tuned amplifiers, mixers, oscillators, phase shifters and detectors. Communications systems considered are AM, FM, television and telephony. Use of the PLL will be discussed.

Course Content

  1. Introduction to Telecommunications: Components of a radio systems; noise, distortion impedance matching.

  2. Mixers and Modulators:

  3. Phase-Locked Loop and Applications: Introduction to PLLs and applications such as: synthesizers and FM demodulation.

  4. Oscillators:

  5. Frequency modulators and demodulators:

  6. Television Systems: Transmission of intensity, color, retrace, blanking, and sound; generation of the video signal, conversion of the video signal to picture and sound. Other topics may include high-definition TV, stereo sound.

Labs

Simulation Labs - Groups of 1; Hardware Labs - Groups of 2, one writeup per group, due one week after the scheduled lab day, 4:30 PM.
  1. Tuned Amplifiers: (Dates removed, these were 2000) (September ??, ??, ??). Simulation Lab. Use of a bipolar transistor and some passive components to build a tuned amplifier operating at about 1MHz. You will learn about use of transistor parameters, tuned circuits and impedance matching.

  2. Mixers and Modulators: (October ??, ??, ??) Use of an analog multiplier on an IC to build frequency changers.

  3. Phase-Locked Loops: (November ??, ??, ?? and ??, ??, ??) Use of a commercially available package to build a tracking filter, a synthesizer and a an FM demodulator. The IC contains a voltage-controlled oscillator a phase detector, and amplifiers. In this lab, the VCO and phase detector will be characterized, then a complete phased-lock loop will be built. The main external components will consist of a simple loop filter and a divider to realize the synthesizer.

Marks:

a) Three assignments worth 5% each
b) Three Labs worth 10, 10,15 (about 1/3 for demo)
c) One written exam worth 50%.
**** Students must get at least 35% in the final exam. ****

Text:

There is no official course text. The printed course notes should provide enough material, or some of the references can be consulted.

References: