The following calendar lists votes for exam review sessions
(with second choice getting 0.7 vote). In the end, since Friday
5:30 and Monday 1:00 were both popular, reviews were held on
both days. I didn't prepare problems to solve, instead, students
put in requests and I went over these.
Review Sessions: The first review session was on Friday Dec 17
5:30 in the room next to the IEEE. We went over two noise questions
(2003, #1e, 2000 #2) one PLL question (2003 #5) and a mixer question
(2003 #4). There were about 35 attendees (about half the class).
The next review session was Monday 1:15 MC 5050 - more than half
the class was there - an excellent turnout.
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
5
6
7
8
9
10
11
12
13 Office Hour 10-11
14
15 Meetings ~9:30 - 3:00
16
0.7 Votes
17 Thesis 9-12 16.4 Votes (9.4 for after 5)
18 3509 Rev 1-4 4.8 Votes
19
0.7 Votes
20 3509 Exam 9-12 14.1 Votes
21 1 Vote
22 4505 Exam 2-5
23 Too Late (Marking)
24 Too Late (Marking)
25 Merry Christmas
26 Marking ELEC 3509
27 Marking ELEC 3509
28 Marking 4505 Q1
29 Marking 4505 Q2
30 Marking 4505 Q3
31 Marking 4505 Q4, Q5
Jan 1, 2005 Marking 4505 Q5
Jan 2, 2005 Marking 4505 Q6
Jan 3, 2005 Submit Marks ELEC 4405
Jan 4, 2005 Sleep In
Jan 5, 2005 Prepare for Winter Term
Jan 6, 2005 First Lecture ELEC 5503
Jan 7, 2005
Jan 8, 2005
Marks as of Dec 8. Please verify and let me know of any
problems. Also, marked assignment 3 now available to be picked
up.
the PLL transient reponse plot has been made larger.
lock range for an X-Or gate has been added.
Corrections have been made to the distortion section
output power proportional to input power, instead of
output voltage proportional to input power,
IM3 proportional
to the cube of input power, rather than 3 times input power.
PLL loop filter defined as F(s) rather than A0 F(s), since
the following equations will still work even if there is an additional
A0. Often A0 = 1, but it doesn't have to be.
Thursday Dec 2 we will continue with review of
the 1998 Final Exam (pdf). Please eamil me with any requests
for other problems to solve.
Office Hours week of Nov 8-12: Peter Popplewell, Friday 2:30-3:30
Final Exam, Wednesday December 22, 2:00-5:00, Southam Hall
Please feel free to email me
with questions, I will attempt to answer them by email, but will
also post them here.
Also, click here for questions and answers from
2003. Further links to questions, answers from earlier years
can also be found (check links to previous years, below).
Lab 2 Due Date Extended: now due 4:30 Monday Oct 25,
Tuesday Oct 26, Wednesday Oct 27 for students whose labs were
scheduled for Wednesday, Thursday, Friday, respectively.
Assignment 1 Due : In Class, Oct 12 (After Thanksgiving)
Monday Oct 11 is Thanksgiving, this is a holiday
Is Friday Oct 8 a Holiday? No, classes are suspended, but it is
not a holiday.
Labs Due : 4:30 one week after scheduled lab day.
Lab 1, deadline extended to Tuesday, Wednesday, Thursday, nearly
two weeks after scheduled lab day. If you get the lab in by the
original deadline, bonus 5%
Registration
Thursday Sept 16, 10:30 - Carleton Central tells me there is
one spot available in the course.
Announcement about registration: A number of students have
been given permission to register, however, they all need to
fill out the form requesting permission to get into a blocked
section.
Wednesday Aug 11, 75 of 75 spots are filled
Monday Aug 9, 2004, 73 of 75 spots are filled.
Friday Aug 6, 67 of 75 spots filled (8 people signed up after
Friday).
Tuesday Aug 3, registration starts, first 12 people sign up.
Office Hours Monday 10-11, (I will usually also be available
Wednesday 10-11)
Please feel welcome to drop
by to ask questions, make comments, have discussions
on 4505, (or any other topic).
To learn about the design of
communications circuits. In other courses, the block diagram
approach has been used but in this course the emphasis will be
on the actual circuitry which makes up these blocks. Examples
of such blocks are tuned amplifiers, mixers, oscillators, phase
shifters and detectors. Communications systems considered are
AM, FM, television and telephony. Use of the PLL will be discussed.
Course Content
Introduction to Telecommunications:
Components of a radio systems; noise, distortion impedance matching.
Mixers and Modulators:
Phase-Locked Loop and Applications:
Introduction to PLLs and applications such as:
synthesizers and FM demodulation.
Oscillators:
Frequency modulators and demodulators:
Television Systems:
Transmission of intensity, color, retrace, blanking, and sound;
generation of the video signal, conversion of the video signal
to picture and sound. Other topics may include high-definition
TV, stereo sound.
Labs
Simulation Labs - Groups of 1; Hardware Labs - Groups of 2, one
writeup per group, due one week after the scheduled lab day, 4:30 PM.
Tuned Amplifiers: (Dates tentative)
(Warmup on September 15, 16, 17 actual lab on 29, 30, October
1). Simulation Lab. Use of a bipolar transistor and some passive
components to build a tuned amplifier operating at about 1MHz.
You will learn about use of transistor parameters, tuned circuits
and impedance matching.
Mixers and Modulators:
(October 13, 14, 15) Use of an analog multiplier on an IC to
build frequency changers.
Phase-Locked Loops:
(October 27, 28, 29 and November 10, 11, 12) Use of a commercially
available package to build a tracking filter, a synthesizer and
a an FM demodulator. The IC contains a voltage-controlled oscillator
a phase detector, and amplifiers. In this lab, the VCO and phase
detector will be characterized, then a complete phased-lock loop
will be built. The main external components will consist of a
simple loop filter and a divider to realize the synthesizer.
Marks:
a) Three assignments worth 5% each
b) Three Labs worth 10, 10,15 (about 1/3 for demo)
c) One written exam worth 50%.
**** Students must get at least 35% in the final exam. ****
Text:
There is no official course text. The printed course notes should
provide enough material, or some of the references can be consulted.
References:
Smith,
"Modern Communication Circuits", Second Edition McGraw-Hill 1998, TK6553.S5595
Krauss, Bostonian, Raab,
"Solid State Radio Engineering", Wiley 1980, TK6553.K73
Rogers and Plett,
"Radio Frequency Integrated Circuit Design", Artech House 2003
Hagen,
"Radio Frequency Circuit Design", Cambridge Press, 1997
William F. Egan,
"Frequency Synthesis by Phase Lock", 2nd Ed. John Wiley & Sons,
2000
Van der Puije,
"Telecommunication Circuit Design", Wiley 1992, TK5103.V