Advanced Verilog, test benches. VLSI design based on CMOS technology, characteristics of CMOS logic circuits, cell libraries, building blocks, structured design, testing, Computer-Aided Design tools. Laboratory emphasis on design synthesis from Verilog.
Prerequisite(s): fourth-year status in Engineering and ELEC 3500 or permission of the Department.
Lectures three hours a week, laboratory and problem analysis three hours alternate weeks.