The conventional on-chip interconnect copper material is unable to meet the requirements of future technology needs, since it demonstrates lower reliability with down scaling of interconnect dimensions. Therefore, researchers are forced to find an alternative solution for interconnects. Graphene nano interconnects have been proposed as promising interconnect materials due to their unique physical properties such as higher thermal conductivity, current carrying capability and mechanical strength. Graphene nano interconnects can be classified into carbon nanotubes (CNT) and graphene nanoribbons (GNR). CNTs are made by rolling up of graphene sheet in a cylindrical form and GNR is a strip of ultra-thin width graphene layer. Most of the physical and electrical properties of GNRs are similar to that of CNTs, however, the major advantage of GNRs over CNTs is that both transistor and interconnect can be fabricated on the same continuous graphene layer. Therefore, one of the manufacturing difficulties in formation of perfect metal-nanotube contact can be avoided. On other hand, the GNRs fabricated till date, have displayed some level of edge roughness. The electron scattering at rough edges reduces the mean free path (MFP) that substantially lowers the conductance of the GNR. This fundamental challenge limits the performance of GNR interconnects. Presently, researchers and industrialists are standing at crossroads where they need to make subtle improvements to make CNTs and GNRs a workable solution for future.
The conventional planar integrated circuit (2D) packaging technique has already hit the red brick wall and is almost on the verge of extinction due to limited number of I/O pins and lower bandwidth. The best way to move towards the “More-than-Moore” technologies is 3D IC packaging, where the dies are vertically stacked. The electrical connections between the dies are established by through silicon vias (TSVs). The idea of using CNTs and GNRs as filler material in TSVs has also rapidly gained research interests. Considering the above-mentioned issues, this talk will analyze and compare the performance of CNTs and GNRs for both on-chip interconnects and TSVs applications.
Brajesh Kumar Kaushik received Doctorate of Philosophy (Ph.D.) in 2007 from Indian Institute of Technology, Roorkee, India. He joined Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, as Assistant Professor in December 2009; and since April 2014 he has been an Associate Professor. He has served as General Chair, Technical Chair, and Keynote Speaker of many reputed international and national conferences. Dr. Kaushik is a Senior Member of IEEE and member of many expert committees constituted by government and non-government organizations. He is Editor of IEEE Transactions on Electron Devices; Associate Editor of IET Circuits, Devices & Systems; Editor of Microelectronics Journal, Elsevier; Editor of Journal of Electrical and Electronics Engineering Research, Academic Journals; and Editorial board member of Journal of Engineering, Design and Technology, Emerald. He also holds the position of Editor-in-Chief of International Journal of VLSI Design & Communication Systems, and SciFed Journal of Spintronics & Quantum Electronics. He has received many awards and recognitions from the International Biographical Center (IBC), Cambridge. His name has been listed in Marquis Who’s Who in Science and Engineering® and Marquis Who’s Who in the World®. Dr. Kaushik has been conferred with Distinguished Lecturer award of IEEE Electron Devices Society (EDS) to offer EDS Chapters with quality lectures in his research domain. His research interests are in the areas of high-speed interconnects, low-power VLSI design, memory design, carbon nanotube-based designs, organic electronics, FinFET device circuit co-design, electronic design automation (EDA), spintronics-based devices, circuits and computing, image processing, and optics & photonics based devices