Efficient hardware implementation of complex algorithms

Dr. Carlo Condo
Friday, August 28, 2020


He is currently a researcher at the Huawei Paris research center, where he successfully designed and implemented innovative error-correction solutions for high-performance, low-power, high-speed future optical communication systems. Previously he was a postdoctoral fellow at McGill University and, before that, a PhD student at Politecnico di Torino. He has  published 28 journal papers, 31 conference papers, one book chapter and obtained six patents and is an associate editor for IEEE Transactions on Emerging Topics in Computing, IEEE Transactions on Circuits and Systems II, and IEEE Communications Letters, and a reviewer for many IEEE publications of the Circuits and Systems, Signal Processing, Computer, Communications and Information Theory societies. 


Many fields of application require computationally intensive algorithms to be implemented on dedicated digital circuits, in order to meet stringent throughput and latency metrics. At the same time, area and power constraints limit the available resources and demand substantial optimization efforts and careful design, leading to a complicated game of priority juggling and trade-offs. In this presentation, I will show how my research on forward error correction for communications and deep neural networks, has tackled the issue through hardware-aware algorithm optimization, and through algorithm-aware hardware design. Current academic and industrial trends point at the growing importance of optimized hardware design in the emerging edge computing scenario, and I will overview some directions that I would love to follow with the department.

Contact: Tom.Smy@carleton.ca for more details.

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